1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to a substantially planarized interconnect topography and method for making spaced interconnect by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect structure and a series of relatively narrow interconnect structures.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the implant regions from overlying conducting regions. Interconnect routing is then patterned across the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparities develop across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Also, stringers may arise from incomplete etching over severe steps. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational “hill” or “valley” area. The presence of such elevational disparities therefore makes it difficult to print high resolution features.
Techniques involving chemical and mechanical abrasion (e.g., chemical-mechanical polishing) to planarize or remove the surface irregularities have grown in popularity. As shown in FIG. 1, a typical chemical-mechanical polishing (“CMP”) process involves placing a semiconductor wafer 12 face-down on a polishing pad 14 which lies on or is attached to a rotatable table or platen 16. A popular polishing pad medium comprises polyurethane or polyurethane-impregnated polyester felts. During the CMP process, polishing pad 14 and semiconductor wafer 12 may be rotated while a carrier 10 holding wafer 12 applies a downward force F upon polishing pad 14. An abrasive, fluid-based chemical suspension, often referred to as a “slurry”, is deposited from a conduit 18 positioned above pad 14 onto the surface of polishing pad 14. The slurry may fill the space between pad 14 and the surface of wafer 12. The polishing process may involve a chemical in the slurry reacting with the surface material being polished. The rotational movement of polishing pad 14 relative to wafer 12 causes abrasive particles entrained within the slurry to physically strip the reacted surface material from wafer 12. The pad 14 itself may also physically remove some material from the surface of the wafer 12. The abrasive slurry particles are typically composed of silica, alumina, or ceria.
CMP is commonly used to form a planarized level of an integrated circuit containing interconnect laterally spaced from each other in what is generally referred to as the “damascene” process. Laterally spaced trenches are first etched in an interlevel dielectric configured upon a semiconductor topography comprising electrically conductive features. A conductive material is then deposited into the trenches and on the interlevel dielectric between trenches to a level spaced above the upper surface of the interlevel dielectric. CMP is applied to the surface of the conductive material to remove that surface to a level substantially commensurate with that of the upper surface of the interlevel dielectric. In this manner, interconnect that are isolated from each other by the interlevel dielectric are formed exclusively in the trenches. CMP can planarize only localized regions of the interconnect surface such that all interconnect traces have a co-planar upper surface, provided certain conditions are met. The localized area must contain trenches that are consistently, and closely spaced from each other. Moreover the trenches must be relatively narrow in lateral dimension. If those rather restrictive requirements are not met, then thicknesses of a given interconnect layer can vary to such a degree that local regions of interconnect may suffer severe current carrying limitations.
In particular, planarization may become quite difficult in a region where there is a relatively large distance between a series of relatively narrow interconnect, or if there is a relatively wide interconnect such as that found in, for example, a bond pad. FIGS. 2-4 illustrate a typical damascene process and the localized thinning or “dishing” problem experienced by conventional metal CMP processes.
As shown in FIG. 2, a series of relatively narrow trenches 22 and a relatively wide trench 24 are formed in an interlevel dielectric 20 using well-known lithography and etch techniques. The series of narrow trenches 22 and the wide trench 24 are laterally separated by a region of interlevel dielectric having a smooth upper surface 26. FIG. 3 illustrates a conductive material 28, e.g., a metal, such as Al, W, Ta, and Ti, deposited across the topography to a level spaced above upper surface 26. Due to the conformal nature of the sputter or CVD process used to apply the conductive material, the conductive material takes on an upper surface topography having a first region 30 formed over closely spaced hill and valley areas spaced above the series of narrow trenches 22. The topography also includes a second region 32 having a single wide valley area spaced above the wide trench 24 and a substantially flat third region 34 spaced above smooth upper surface 26. Conductive material 28 is then polished, as shown in FIG. 4, using CMP to remove conductive material 28 from the upper surface of interlevel dielectric 20. As a result of CMP, a series of relatively narrow interconnect 36 are formed exclusively in narrow trenches 22 and a relatively wide interconnect 38 is formed exclusively in wide trench 24. The narrow interconnect 36 may serve to electrically connect underlying active devices and conductive elements of the semiconductor topography. The wide interconnect 38 may subsequently function as, e.g., a bond pad.
Unfortunately, the topological surface of the interconnect level is not absent of elevational disparity. That is, the upper surface of interconnect 38 includes a recessed area 42 that extends below a substantially planar upper surface 44 of interlevel dielectric 20. Recessed area 42 may result from a phenomena known as the “dishing” effect. Dishing naturally results from the polishing pad flexing or conforming to the surface being polished. If the surface being polished is initially bowed or arcuate (i.e., is not planar), the polishing pad will take on the shape of the non-planar regions causing further dishing of the surface being polished. The CMP slurry initiates the polishing process by chemically reacting with the surface material in both elevated and recessed areas. Because of the deformation of the CMP pad, the reacted surface material in recessed areas may be physically stripped in addition to the reacted surface material in elevated areas. As such, a surface having fluctuations in elevation may continue to have some elevational disparity even after it has been subjected to CMP. The dishing effect is particularly a problem when forming a relatively wide interconnect between regions of a dielectric that is substantially more dense than the metal. While the dielectric is hard enough to support the overlying regions of the CMP pad, the metal is not, and thus allows significant flexing of the pad. Such flexing of the CMP pad causes the surface of the metal interconnect to become recessed relative to adjacent regions of the dielectric.
In addition, the topological surface includes a recessed area 40 arranged over the set of narrow interconnect 36. It is believed that such a recessed area 40 forms due to so-called “oxide erosion” of interlevel dielectric 20, assuming that the dielectric is composed of silicon oxide. The CMP slurry chosen to polish the metal of the interconnect includes a chemical component that reacts with metal at a faster rate than with oxide. As such, even after the metal surface has been removed to a level commensurate with that of the oxide surface, its removal may continue at a faster rate than that of the oxide. The metal surface thus becomes spaced below that of the oxide, creating steps in the topological surface. At this point, the relatively small, elevated oxide regions are removed by the CMP pad at a faster rate than large area oxide regions, or even the adjacent, recessed metal regions. Because the oxide outside the area comprising the densely packed interconnect has no elevational disparity, its removal rate is relatively slow. Therefore, the oxide in the dense interconnect area becomes recessed below the oxide outside the dense interconnect area.
It would therefore be desirable to develop a polishing process which can achieve global planarization across the entire topological surface of an interconnect level. Global planarization requires that the polish rate be uniform in all elevated areas of the topography. Such uniformity of the polish rate is particularly needed when polishing a topography having a set of interconnect which is of relatively narrow lateral dimension spaced from a relatively wide interconnect. Herein, narrow and wide refer to a lateral dimension which extends along the trench base perpendicular and co-planar with the elongated axis of the interconnect. That is, the dielectric in the space between the series of narrow interconnect and the wide interconnect needs to be polished as quickly as the interconnect are polished in order to assure both densely spaced narrow interconnects and sparsely spaced wide interconnects have a flat and relatively co-planar upper surface. The desirous polishing process must avoid problems typically arising during CMP, for example, metal dishing or oxide erosion.